1. Field of the Invention
The present invention relates to semiconductor integrated circuits and particularly memory devices.
2. Description of the Related Art
A memory device (or core) is known to comprise an array of memory cells, a word decoder, sense amplifiers including input/output buffers for temporary storing the data read/written from/in the memory array and a control logic.
Traditionally, to read a digital datum contained in a cell of the memory array (e.g. a SRAM cell), the control logic sends enable signals to the word decoder such as to command the turning on of word lines relating to the cell to be read.
It should be observed that known memory devices provide a synchronization signal or clock signal external to the memory to activate the control logic. For example, this control logic starts the enable signals of the word decoder at a rising edge of the clock signal.
As is well known to those skilled in the art, the memory cell to be read comprises bit lines that are conventionally precharged at a reference voltage upon each read operation.
Whereby, after the word lines of the cell to be read have been turned on, a differential voltage signal is generated between the bit lines in the cell. This differential signal is caused by the discharge of one of them.
At a preset voltage value of the differential discharge signal, the input/output buffers are enabled to output the datum read by the memory.
After the datum has been outputted, another precharge of the cell bit lines is provided for preparing the memory for a subsequent read operation.
In this case, a new rising edge of the clock signal, corresponding to the subsequent reading operation, can activate the control logic only after this bit line precharge has finished.
Accordingly, the conventional memory devices have a too long cycle time (the time between two subsequent clock edges), i.e. they are too slow and inadequate in a number of applications.